The present invention relates to an information reproduction apparatus provided with a capability of performing error correction processing and error detection processing on input data.
Random errors or burst errors often occur to data read from a CDROM, a DVD or the like due to noises or disk scratches. Accordingly, error correction processing and error detection processing are carried out by use of error correction codes and error detection codes to obtain correct data.
FIG. 9. shows a data structure in DVD. One sector is comprised of a 2366-byte code including 2048-byte main data to which a header, an EDC (Error Detection Code), and an ECC (Error Correction Code) are attached. As shown in FIG. 10, one sector consists of 26 frames. Accordingly, as shown in FIG. 11, the period of a frame synchronization signal is one twenty sixth the period of a sector synchronization signal.
FIG. 12 shows a structure of an error correction block in DVD. As shown in this figure, one 32-KB (kilobyte) error correction block is formed as a product code from 16 sectors. The error correction processing on the error correction block is comprised of a first error correction (horizontal correction) and a subsequent second error correction (vertical correction). Even when there are some codes that could not be corrected by carrying out the first error correction, they can be corrected by carrying out the second error correction if they are smaller in number than a certain value.
After the first error correction and the second error correction are completed for the whole of the error correction block, data descrambling is carried out, and subsequently the error detection processing is carried out on a sector-by-sector basis by use of EDCs. As described in Japanese Unexamined Patent Publication No. 180379-97 for example, it is also known that an interval between two successive synchronization signals of two consecutive sectors is compared with a reference interval to detect errors with the aim of dispensing with a specific error detection circuit that detects errors by use of EDCs.
FIG. 13 shows a structure of an information reproduction apparatus provided with a conventional error correction/detection capability for reproducing information from a disk (DVD). In FIG. 13, 100 denotes a disk, 101 denotes a head amplifier, 104 denotes a memory, 113 denotes a controller, 114 denotes a servocontroller, and 120 denotes a signal processing unit. The signal processing unit 120 includes a demodulator 102, a memory write device 103, a block synchronization signal producing device 105, a counter 106, a sequencer 107, an error corrector 108, a first memory read/write device 109, an error detector 110, a second memory read/write device 111, a data read device 116, and a data output device 115. The functions of the above-described elements of the information reproduction apparatus will be explained below.
The head amplifier 101 reads signals from the disk 100, and converts them into digital signals. The demodulator 102 demodulates the digital signals to produce data constituting a part of a code word, and also produces sector synchronization signals. The memory write device 103 writes the demodulated data into the memory 104. The memory 104 holds the demodulated data, as well as data after the error correction processing, data that has undergone the descrambling and the error detection processing, and data to be output to the outside. The block synchronization signal producing device 105 produces a block synchronization signal from the sector synchronization signals output from the demodulator 102 for each error correction block formed from 16 sectors. The counter 106 is initialized by the block synchronization signal output from the block synchronization signal producing device 105, and updates its count value when the error corrector 108 completes error correction in each correction mode (the first error correction mode, or the second error correction mode).
The sequencer 107 sets the mode, in which the error corrector 108 operates, based on the count value of the counter 106. The error corrector 108 accesses the memory 104 by way of the first memory read/write device 109 to read or write data, and performs the first or the second error correction following instructions from the sequencer 107. The error corrector 108 also outputs a signal indicative of the error correction in each mode having been completed, this signal being counted by the counter 106. The first memory read/write device 109 accesses the memory 104 in accordance with a request from the error corrector 108.
The error detector 110 access the data that has undergone the first error correction and the second error correction and is held in the memory 104 by way of the second memory read/write device 111, and carries out the descrambling to detect errors on a sector-by-sector basis by use of EDCs. The error detector 110 outputs an error detection signal to the controller 113 when detecting an error. The servocontroller 114 performs a disk rotation control for reading data from the disk 100, and a tracking control of a pickup. The data output device 115 reads data held in the memory 104 by way of the data read device 116 in accordance with a request from the outside, and outputs the data to the outside. The controller 113, which is for controlling the entire operation of the information reproduction apparatus, commands the servocontroller 114 to read again the error correction block that has been detected to have an error, upon receipt of the error detection signal from the error detector 110.
The operation of this apparatus will be explained below with reference to a timing chart shown in FIG. 14 for a case where there exists an uncorrectable code in the M-th sector within an error correction block read from the disk 100 and written into the memory 104. FIG. 14 shows the sector synchronization signal output from the demodulator 102, the block synchronization signal output from the block synchronization signal producing device 105 for each error correction block, a logical state of the sequencer 107, a count value of the counter 106, and addresses of spaces within the memory 104 which are accessed by the memory write device 103, the first memory read/write device 109, and the second memory read/write device 111 respectively.
Signals recorded in the disk 100 are read by the head amplifier 101, converted into digital form, and supplied to the demodulator 102. The demodulator 102 writes demodulated data into the memory 104 by use of the memory write device 103, while outputting sector synchronization signals to the block synchronization signal producing device 105. The block synchronization signal producing device 105 produces the block synchronization signal from the sector synchronization signals. The counter 106 is initialized by the block synchronization signal output from the block synchronization signal producing device 105 to have the initial count value of xe2x80x9c1xe2x80x9d for example. The sequencer 107 outputs, to the error corrector 108, a signal which stays at xe2x80x9cLxe2x80x9d level during a period over which the error correction processing is performed, and a signal which is at xe2x80x9cHxe2x80x9d level when causing the error corrector 108 to perform the first error correction and at xe2x80x9cLxe2x80x9d level when causing the error corrector 108 to perform the second error correction. The error corrector 108 corrects errors in the data within the memory 104 by use of the first memory read/write device 109 in accordance with a signal from the sequencer 107. The error detector 110 access the memory 104 holding the data which has undergone the error correction processing by way of the second memory read device 111 to perform error detection processing.
As shown in FIG. 14, assuming that the address of the space holding the data which has undergone the error correction processing is N, the error detector 110 starts to perform the error detection processing on the space of the address N with a block synchronization signal following the block synchronization signal with which the error correction processing was started. The error detector 110 outputs, to the controller 113, a signal which stays at xe2x80x9cLxe2x80x9d level during a period over which the error detection processing for 16 sectors is performed, and an error detection signal which is at xe2x80x9cHxe2x80x9d level when a sector including an error (that is, the M-th sector) is detected.
It is during execution of the error detection processing following the error correction processing when the error detector 110 outputs the error detection signal to the controller 113. The controller 113 commands, upon receipt of the error detection signal, the servocontroller 114 to start the control for reading again the error correction block including the sector which has been detected to have an error.
As described above, the conventional information reproduction apparatus is configured to execute the second error correction subsequent to the first error correction irrespective of the result of the first error correction (the number of uncorrectable code words), and to check the presence or absence of errors on sector-by-sector basis by use of EDCs after completion of the entire error correction processing for one error correction block. Accordingly, there is a large time lag between a moment at which an error correction block read from the disk is written into the memory and a moment at which the block is read again from the disk because the block is recognized to include a sector that has a code word that could not be corrected by performing the first error correction. Therefore, since there are many sectors which the servocontroller has to retrace to read the block again, the control becomes difficult and a long stabilization period is required. Furthermore, when it takes a long time to read the block including a sector that has been detected to have an error for the second time, the memory runs out of data to be output to the outside through the data output device, and thereby data output discontinues.
On the other hand, in the information reproduction apparatus that is configured to measure the interval of sector synchronization signals and recognize existence of an error when the measured interval is different from a reference interval, there is a possibility that errors which could be corrected by completing the error correction processing dedicated to a product code are determined as uncorrectable, and needless rereading of data is carried out.
The present invention has been made to solve the above problems with an object of providing an information reproduction apparatus capable of detecting errors at an early stage with high accuracy without using EDCs.
The object is achieved by an information reproduction apparatus including an error corrector which performs a first error correction for correcting errors in a horizontal direction within an input data block comprised of a product code and subsequently a second error correction for correcting errors in a vertical direction within said input data block,
said error corrector producing a first signal each time an uncorrectable code word is detected while said first error correction is being performed;
said information reproduction apparatus further including:
a first counter for counting said first signal;
a comparator for comparing a count value of said first counter with a predetermined value and producing a second signal when said count value reaches said predetermined value; and
a determination device determining that there is an error within said input data block which said error corrector cannot correct, and delivering a third signal to the outside in response said second signal.
The information reproduction apparatus may further include a synchronization signal producing device for producing, from input data constituting an input data block, a synchronization signal used for synchronizing elements within said information reproduction apparatus.
The information reproduction apparatus may further include a synchronizer for delivering said count value of said first counter to said comparator in synchronization with said synchronization signal.
The information reproduction apparatus may further include:
a demodulator for demodulating input data with reference to a table in which a plurality of pieces of data are registered and outputting demodulated data as a part of a code word;
a device for producing a fourth signal when said input data does not match any of said plurality of pieces of data registered in said table;
a second counter for counting said fourth signal; and
a reading device for reading a count value of said second counter and outputting said count value read from said second counter to said first counter;
said first counter counting said first signal only for code words count values on which output from said reading device exceed a predetermined value.
The information reproduction apparatus may further include a data reading device for reading data to be reproduced, said data reading device performing rereading of said input data block in response to said third signal.